DFD Validation

DFD Validation

Location: Bangalore

Job Description

• We are looking for an experienced Debug Tools Engineer with 10\-15 years of experience in DFT, DFD, and Functional Validation domains to drive the development of next\-generation silicon debug infrastructure and tools.
• The candidate will lead the design and implementation of advanced debug solutions including Scan Dump, Array Dump (MBIST), Crash Dump, Hardware Trace, JTAG/TAP Network, and silicon visibility tools used during Pre\-Silicon and Post\-Silicon validation. This role requires deep hardware architecture knowledge and hands\-on experience enabling debug capabilities across complex SoCs and server platforms.

Job Requirement

• Debug Tool Development – State dump
• Develop and maintain debug tools for: Scan Dump and Scan Analysis,Array Dump / MBIST Debug
• Hardware Trace and Trigger Infrastructure
• Crash Dump Collection and Analysis
• JTAG/TAP Network and Boundary Scan Tools
• Register Access and Silicon Visibility Frameworks

Required Skills

• 10\-15 years of experience in DFT/DFD and silicon debug.
• Strong understanding of Scan Compression Architectures
• MBIST and Memory Diagnostics
• JTAG/TAP Protocols
• Boundary Scan (BSCAN)
• Hardware Trace Fabrics
• SoC Bring\-up and Debug
• Strong knowledge of server SoC architecture and silicon validation.
• Experience with emulation, simulation, FPGA, and silicon environments.

Experience (years) : 7\-10 years

Education Qualification

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent