Layout Design, Sr Staff Engineer

• *Date posted** 10/28/2026

### **Category** **Engineering****Hire Type** **Employee****Job ID** **19420****Remote Eligible** **No****Date Posted** **10/28/2026**

### **We Are**Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI\-powered products. We deliver industry\-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R\&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

### **You Are**

You have spent years in the trenches of physical design, where a misplaced power ring or a routing bottleneck can turn a promising memory macro into a timing nightmare. Layout is not just drawing rectangles to you, it is solving a puzzle where every micron counts and every decision ripples through verification, performance, and yield. You know that the difference between a memory compiler that ships and one that gets stuck in debug is usually a floor plan decision made two weeks earlier, and you are the kind of engineer who sees that coming.

You are comfortable moving between Calibre or ICV verification runs, XARA power analysis, and sitting with circuit designers to understand why a bitcell is behaving the way it is. When a DRC violation shows up at tape\-out minus two days, you do not panic, you methodically trace it back, fix it, and document it so it does not happen again. You have strong opinions about power grid design and you can back them up with IR drop numbers.

At Synopsys, you will work on memory IP that goes into chips powering everything from AI accelerators to automotive systems. The layouts you own will be used by customers worldwide, and the quality bar is exactly as high as you would expect.

### **What You'll Be Doing**

• Design and own full custom layouts for embedded memory blocks, including SRAM, register files, and ROM compilers across advanced process nodes
• Develop floor plans, place memory cells and periphery blocks, route power grids and signal interconnects to meet area, performance, and power targets
• Run IR drop and electromigration analysis using tools like XARA, back\-annotate layout parasitics, and iterate with circuit teams to close timing and power
• Execute physical verification using DRC and LVS tools such as ICV or Calibre, debug violations, and drive layouts to clean signoff
• Collaborate with memory compiler architects and circuit designers to translate specifications into manufacturable, verified layout deliverables
• Script layout automation flows using TCL, Perl, or C\-shell to improve productivity and ensure consistency across memory variants
• Support formal release cycles, including documentation, design rule checks, and handoff to product engineering and customers

### **The Impact You Will Have**

• Enable Synopsys memory IP to meet aggressive PPA targets that directly affect customer chip performance and power efficiency
• Reduce layout development cycle time through automation and reusable design practices, accelerating time to market for new memory products
• Ensure memory macros pass physical verification and reliability checks on the first pass, minimizing costly respins and customer escalations
• Contribute to the quality and competitiveness of Synopsys memory compiler offerings used in high\-volume production across automotive, mobile, and AI markets
• Influence layout methodology and best practices that shape how the team approaches next\-generation process nodes
• Mentor junior layout engineers and