- *Date posted** 05/31/2026
### **Category** **Engineering****Hire Type** **Employee****Job ID** **17664****Remote Eligible** **No****Date Posted** **05/31/2026**
### **We Are**
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI\-powered products. We deliver industry\-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R\&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
### **You Are**
You have spent years in the trenches of analog and mixed signal layout, where a misplaced via or a poorly shielded signal path can kill months of circuit design work. You know that high\-speed SerDes layout is not just about following DRC rules, it is about understanding what actually happens when a 56Gbps signal hits a corner you drew at 2am. You see EM violations before the tool flags them because you have debugged enough tapeout failures to know where they hide.
Working in advanced nodes does not intimidate you. FinFET effects, deep submicron parasitics, IR drop across power grids, these are problems you have solved, not just read about. You can look at a floorplan and know whether it will close, and you are not afraid to push back when a circuit designer hands you something that will never meet timing or area.
- Design and own physical layout for high\-speed analog and mixed signal IP blocks including SerDes, PLLs, TX/RX circuits, and custom digital logic paths
- Perform full layout verification flow including DRC, LVS, LPE using Calibre, ICV, and STAR\-RXCT to ensure tapeout\-ready quality
- Collaborate directly with analog circuit designers to translate schematics into optimized layouts that meet performance, area, and reliability targets
- advanced floorplanning techniques to manage signal integrity, power distribution, EM/IR constraints, and ESD/latchup mitigation in deep submicron and FinFET processes
- Generate LEFs and support top\-level integration, ensuring your blocks integrate cleanly into larger SoC designs
- Debug complex layout issues using parasitic extraction, simulation correlation, and hands\-on troubleshooting across the full verification stack
- Drive layout automation through scripting to improve turnaround time and consistency across the team
### **The Impact You Will Have**
- Your layouts will directly enable high\-speed SerDes IP that powers data center, automotive, and AI applications shipping in volume production
- Clean, first\-pass layout quality from your work reduces costly respin cycles and accelerates time to market for Synopsys IP customers
- Your deep understanding of FinFET effects and advanced node challenges will help the team navigate complex process technology transitions
- Collaboration with circuit designers ensures that performance targets are met in silicon, not just in simulation
- Your floorplanning and verification rigor will set the standard for layout quality across the analog and mixed signal IP group
- Automation scripts you develop will multiply the productivity of the entire layout team
- Your ability to work independently means the team can scale and take on more complex IP development without bottlenecks
### **What You'll Need**
- Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering
- 6\+ years of hands\-on experience in analog and mixed signal custom IC layout, with specific exposure to high\-speed analog circuits
- Proven experience with Custom Designer or Cadence Virtuoso for layout design
- Strong working knowledge of Calibre, ICV, and STAR\-RXCT for DRC, LVS, and parasitic extraction
- Solid understanding of CMOS and FinFET layout techniques, deep submicron effects, and mitigation strategies
- Experience with layout verification flow including LEF generation, top\-level integration, EM/IR analysis, and DFM considerations
Familiarity with ESD and latchup layout design rules and how to* them in real designs is a strong plus
### **Who You Are**
- You can look at a schematic and immediately start thinking about device matching, shielding strategy, and how parasitics will affect circuit performance
- When a DRC violation shows up at 4pm before tapeout, you do not panic, you methodically trace it back, understand the root cause, and fix it without breaking LVS
- You communicate clearly with circuit designers, explaining layout tradeoffs in terms they care about without needing three meetings to get alignment
- Ownership comes naturally to you, if you say a block is ready for integration, the team knows it has been checked, verified, and will not come back with surprises
- You are comfortable working independently on your day\-to\-day tasks but know when to pull in a colleague or escalate a risk before it becomes a problem
- Scripting for layout automation is something you see as a force multiplier, not a distraction, and you look for opportunities to eliminate repetitive manual work
### **The Team You'll Be Part Of**
You will join the Analog and Mixed Signal IP group, working with a team of custom layout design engineers focused on SerDes and high\-speed analog IP blocks. This is a collaborative team where layout engineers work closely with circuit designers to deliver production\-quality IP that ships to customers globally.
### **Rewards and Benefits**
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non\-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.