Lead Engineer - Emulation

LNT/LE\-E/1904140

• LTST\-L\&T Semiconductor Technologies Limited
• Bengaluru
• Posted On 23 Oct 2026
• End Date 21 Apr 2027
• Required Experience11 \- 16 years

• *Skills**
• ---------

#### **Knowledge \& Posting Location**

FPGA

#### **Minimum Qualification**

Bachelor of Technology (BTech)

• *Job Description**
• ------------------

• *Role**

Provide technical leadership for FPGA\-based SoC prototyping and emulation, with primary ownership of complex multi\-FPGA prototyping, partitioning, FPGA implementation, timing closure, board bring\-up and system\-level debug. Drive FPGA emulator\-based validation using platforms such as HAPS\-100, ZeBu and Veloce, while establishing methodologies, automation and optimization strategies to improve capacity, performance, debug efficiency and pre\-silicon validation TAT. Serve as the technical authority and escalation point for complex FPGA prototyping and emulation challenges.

• *Key Responsibilities**

• **Lead end\-to\-end FPGA prototyping and emulation** of complex SoC/ASIC designs, covering RTL readiness, synthesis, partitioning, P\&R, bitfile generation, hardware bring\-up, validation and system\-level debug.
• Own and drive **multi\-FPGA prototyping** for large and complex SoC designs using platforms such as **HAPS, Protium and other FPGA\-based prototyping systems**, with strong focus on capacity, performance and scalability.
• Drive **emulator\-based validation** on platforms such as **ZeBu and Veloce**, including model bring\-up, compilation, partitioning, debug, performance optimization and integration with DV/SV/FW environments.
• Provide technical leadership in selecting and optimizing the appropriate **FPGA prototyping vs. emulator strategy** based on design size, debug requirements, performance, software execution and validation objectives.
• Lead **multi\-FPGA partitioning and interconnect optimization**, addressing FPGA resource utilization, pin multiplexing, routing congestion, cross\-FPGA communication and partition\-level timing challenges.
• Own **FPGA timing closure** for complex multi\-clock SoCs, including clock architecture analysis, clock/reset adaptation, constraint development, timing analysis and resolution of critical timing paths.
• Lead **FPGA board bring\-up and system integration**, including clocks, resets, JTAG, memories and key interfaces such as **SPI, I2C, UART, MDIO, PCIe and other SoC interfaces**.
• Drive **prototype/emulator model bring\-up and debug**, using FPGA probes, waveform/debug tools and hardware/software correlation to identify issues across RTL, FPGA implementation, hardware and firmware.
• Analyze **RTL\-to\-netlist implementation**, identify synthesis and implementation challenges, and work with RTL/design teams on modifications required for successful FPGA prototyping and emulation.
• Optimize **synthesis and P\&R flows** to improve FPGA QoR, timing, utilization and build/compile turnaround time.
• Define and establish **FPGA prototyping and emulation methodologies, flows and best practices** to improve model bring\-up, debug efficiency and overall pre\-silicon validation TAT.
• Lead evaluation of **next\-generation FPGA prototyping and emulation platforms**, assessing capacity, performance, compile time, debug capability, scalability and suitability for future SoC programs.
• Drive **tool and flow validation** across FPGA synthesis, P\&R and prototyping/emulation environments, working closely with EDA/tool development teams on new features, stability and performance improvements.
• Develop **automation and productivity solutions** using TCL/Perl/Python to automate FPGA builds, partition analysis, regression, QoR extraction, timing analysis, log analysis and result correlation.
• Establish metrics and continuously optimize **FPGA build time, emulation compile time, runtime performance, resource utilization, timing, capacity and overall prototyping/emulation turnaround time**.
• Serve as the **technical escalation point** for complex FPGA prototyping and emulation issues, driving root\-cause analysis and resolution across FPGA, RTL, tools, hardware and software domains.
• Collaborate closely with **Architecture, Design, DV, SV, Firmware, Software, Board and EDA teams** to ensure smooth transition from RTL to FPGA prototype/emulator and accelerate pre\-silicon validation.
• Provide **technical leadership and mentoring** to engineers in FPGA architecture, multi\-FPGA partitioning, synthesis/P\&R, timing closure, board bring\-up, emulator flows and debug methodologies.
• Drive technical reviews with senior stakeholders, providing **status, technical risks, dependencies, mitigation plans and execution strategy** for major FPGA prototyping and emulation programs.