- *Date posted** Jun. 15, 2026
- *Location** Bengaluru, India
- *Category** Software Engineering
15\+ years of experience in **SoC PnP Architecture** within the semiconductor industry, with a strong track record of driving system\-level performance, power, and efficiency investigations across complex silicon platforms.
Strong expertise in **SoC performance architecture and pre\-silicon performance analysis**, including:
- Hands\-on experience with simulation and hardware emulation platforms such as Palladium, Veloce, ZeBu, or equivalent
- Performance analysis using cycle\-accurate, transaction\-level, and emulation\-based environments
- Waveform\-based debug and signal\-level performance analysis
- Latency, bandwidth, throughput, QoS, and utilization characterization
- Transaction\-level tracing and protocol debug across CHI, AXI, PCIe, CXL, or equivalent system protocols
- Identification of system\-level bottlenecks across compute, interconnect, memory, and IO subsystems
- Architectural tradeoff analysis across performance, power, area, latency, bandwidth, and implementation complexity
Strong experience with **SOC Performance and Power modeling methodologies**, including:
- Development and use of **SystemC/TLM, analytical, trace\-driven architecture models**
- Building and calibrating models for **performance, power, latency, bandwidth, utilization, and efficiency analysis**
- **Model\-to\-silicon correlation**, including alignment of pre\-silicon projections, emulation results, and post\-silicon measurements
- Early\-stage architecture exploration to evaluate **performance, power, area, thermal, TDP, and efficiency tradeoffs**
- Using models to guide **SoC architecture decisions, IP configuration, memory/interconnect sizing, QoS strategy, and platform\-level optimization**
- Ability to translate modeling insights into clear architectural recommendations and measurable product improvements
Extensive experience in **post\-silicon performance and power characterization**, including:
- Silicon bring\-up support from a performance and PnP perspective
- Performance counter, PMU, telemetry, and trace\-driven investigations
- Correlation of pre\-silicon projections, architectural models, and silicon measurements
- Root\-cause analysis of performance gaps, power inefficiencies, and workload\-level bottlenecks
- System\-level performance tuning under real silicon constraints
- Analysis of workload behavior under power, thermal, voltage, frequency, and TDP limits
Strong understanding of **SoC system infrastructure and platform\-level PnP behavior**, including:
- Coherent interconnect fabrics and cache\-coherency protocols
- DDR memory subsystems, memory controller behavior, scheduling, QoS, and bandwidth efficiency
- IO subsystems including PCIe, CXL
- Power management architecture, DVFS, clocking, voltage domains, power states, and throttling mechanisms
Proven experience working in both **Linux and bare\-metal environments**, including:
- Performance profiling and debug in Linux\-based systems
- Kernel\-level performance analysis and tracing using perf, ftrace, PMU\-based analysis, or equivalent tools
- Low\-level bring\-up, debug, and performance characterization in bare\-metal environments
- Understanding of boot flows, firmware interactions, BIOS/UEFI or bootloader configuration, and system initialization impacts on performance and power
- Ability to debug issues across hardware, firmware, OS, driver, and workload layers
Strong background in **computer architecture and microarchitecture**, including:
- CPU/GPU/NPU/DSP or accelerator performance behavior
- Pipelines, cache hierarchy, prefetching, coherency, memory systems, and interconnect behavior
- System\-level performance interactions across compute, memory, IO, and power\-management blocks
- Workload characterization and mapping of application behavior to architectural bottlenecks
Proficiency in **C/C\+\+ and Python** for developing
- Performance and power analysis tools
- Automation frameworks
- Profiling and telemetry infrastructure
- Data analysis and visualization dashboards
- Correlation flows across model, emulation, and silicon data
Excellent communication and cross\-functional collaboration skills, with the ability to:
- Clearly present complex performance and power findings to architecture, design, verification, firmware, software, and leadership teams
- Drive data\-based architectural recommendations
- Influence SoC architecture, platform configuration, and product\-level PnP decisions
- Lead investigations across multiple teams and convert debug findings into architectural improvements, tuning proposals, or product guidance
\#LI\-SC2
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