Senior Lead Engineer - Verification

LNT/SLE\-V/1904146

• LTST\-L\&T Semiconductor Technologies Limited
• Bengaluru
• Posted On 23 Oct 2026
• End Date 21 Apr 2027
• Required Experience12 \- 17 years

• *Skills**
• ---------

#### **Knowledge \& Posting Location**

UVM System Verilog \- SV

#### **Minimum Qualification**

Bachelor of Technology (BTech)

• *Job Description**
• ------------------

• *Role**

L\&T Semiconductor Technologies (LTSCT) is seeking an experienced and highly motivated **Senior Lead Engineer, Verification** to play a key technical leadership role in the development of next\-generation semiconductor products.

This position provides an excellent opportunity to build a strong technical career while working on complex, state\-of\-the\-art SoCs and IPs. As a Sr Lead Engineer, you will be responsible for driving verification strategy across **IP, Subsystem, and SoC** levels, leading verification architecture, mentoring engineers, and establishing reusable methodologies that improve quality and engineering productivity.

You will collaborate closely with System Architects, RTL Designers, Physical Design, Analog/Mixed\-Signal, Post\-Silicon Validation, Firmware, and Software teams throughout the product development lifecycle. You will actively participate in architecture reviews, influence design decisions from a verification perspective, and define scalable verification methodologies that enable first\-silicon success.

Your responsibilities will include defining verification strategies, creating reusable SystemVerilog/UVM\-based verification environments, developing comprehensive verification plans, selecting verification tools and methodologies, driving functional and code coverage closure, and ensuring timely project execution with the highest quality standards.

• *Key Responsibilities**

As a Sr Lead Engineer, you will independently lead complex verification activities or provide technical leadership to a team responsible for IP, Subsystem, and SoC verification.

• *Technical Leadership**

• Provide technical leadership for verification projects from architecture definition through verification signoff.
• Operate with a strong product and system\-level mindset, understanding complete data flows and system interactions.
• Drive verification strategy based on product requirements and architecture specifications.
• Define scalable and reusable Testbench (TB) architectures for multiple projects.
• Serve as the Lead Verification Architect for reusable verification environments across product lines.
• Participate in architecture, micro\-architecture, design reviews, and technical decision\-making.

• *Verification Methodology**

• Develop reusable verification environments using **SystemVerilog and UVM** methodologies.
• Create comprehensive Verification Plans, Test Plans, Functional Coverage Plans, Assertions, and Verification Closure Metrics.
• Design and develop reusable Verification IPs (VIPs), Bus Functional Models (BFMs), scoreboards, checkers, monitors, and protocol\-specific verification components.
• Integrate and validate internally developed VIPs with third\-party commercial VIP solutions.
• Drive constrained\-random verification, coverage\-driven verification, assertion\-based verification, and formal verification where applicable.
• Perform environment benchmarking, profiling, optimization, and performance tuning.

• *Verification Execution**

• Plan and execute verification activities from block\-level through full\-chip verification.
• Develop and execute regression strategies for functional, performance, and corner\-case validation.
• Analyze regression results, debug complex failures, identify root causes, and drive timely closure.
• Drive functional, code, assertion, toggle, and FSM coverage closure to meet verification signoff goals.
• Ensure compliance with project quality metrics and verification signoff criteria.

• *Team Leadership**

• Lead and mentor verification engineers across multiple projects.
• Allocate work based on technical complexity, project priorities, and individual strengths.
• Conduct design reviews, code reviews, verification reviews, and technical audits.
• Guide engineers in debugging complex verification issues and adopting industry best practices.
• Foster a culture of technical excellence, innovation, collaboration, and continuous learning.

• *Cross\-Functional Collaboration**

• Work closely with RTL Design, System Architecture, Analog/Mixed\-Signal Design, Physical Design, DFT, Firmware, Software, FPGA Prototyping, Emulation, and Post\-Silicon Validation teams.
• Collaborate effectively with globally distributed engineering teams across multiple geographic locations.
• Interface directly with customers to understand technical requirements, provide engineering solutions, and resolve critical issues with urgency.

• *Methodology \& Productivity Improvement**

• Drive continuous improvements in verification methodologies, engineering processes, and development flows.
• Evaluate, benchmark, and recommend EDA tools, simulators, emulators, formal verification tools, and verification technologies.
• Work closely with EDA vendors to establish efficient verification flows and deployment strategies.
• Develop automation frameworks, regression infrastructure, verification dashboards, and productivity\-enhancing solutions.
• Build automation using scripting languages such as **Python, Perl, Shell, or Tcl** to improve verification efficiency.

• *Documentation \& Knowledge Sharing**

• Prepare verification architecture documents, user guides, methodology documentation, coding guidelines, and verification flow documentation.
• Maintain reusable verification assets and best\-practice documentation.
• Conduct technical seminars, design reviews, methodology workshops, knowledge\-sharing sessions, and internal training programs.

Mentor junior engineers and support their technical and professional growth