As a Senior Mixed Signal Validation and Debug Engineer at Intel Corporation, you will join the Hard IP Development Group (HIPD) within the Central Engineering Organization, which develops leading intellectual properties such as PLLs and various PHYs including DDR/LPDDR, PCIe, USB, TypeC, UCIe Die 2 Die, and Ethernet for servers, clients, networking SOCs, and Intel Foundry customers. Specifically, you will be part of the IO Post Silicon validation debug team, a dynamic group that directly collaborates with IP design teams and SOC customers to validate and debug IPs in test chips and products. Your role will center on swiftly resolving IP-related challenges, driven by a deep commitment to SOC customer obsession, to facilitate successful product deployments and support.