Senior Staff Verification Engineer, High-Speed Interface IP

• *Date posted** 06/11/2026

### **Category** **Engineering****Hire Type** **Employee****Job ID** **17829****Remote Eligible** **No****Date Posted** **06/11/2026**

### **We Are**

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI\-powered products. We deliver industry\-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R\&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

### **You Are**

You have spent years making sure that IP cores actually work, not just in the lab under ideal conditions, but in the real world where timing edges matter and corner cases break things. You know that verification is not about running tests, it is about finding the breaks before they ship, and you have built the instincts to know where to look. You think in coverage metrics and corner cases, but you also understand the bigger picture: the IP you verify powers everything from automotive safety systems to data center connectivity, and getting it right matters.

You are comfortable architecting a verification environment from scratch using SystemVerilog and UVM, and you know how to make those environments scale across multiple engineers and sites. Protocols like MIPI\-I3C, PCIe, USB, and AMBA are not just acronyms to you, you understand their state machines, their edge cases, and what breaks when implementations cut corners. You have debugged enough waveforms to know when a failure is a testbench issue, an RTL bug, or something more subtle in the protocol itself.

You do not wait for perfect specs. You work with what you have, ask the right questions, build coverage models that expose real gaps, and drive closure without losing momentum. At Synopsys, you will work on IP that ships into millions of devices, and the verification environments you build will set the standard for the team.

### **What You'll Be Doing**

• Architect and implement advanced SystemVerilog verification environments for DesignWare high\-speed interface IP cores, including testbenches, checkers, and functional coverage models
• Develop comprehensive test plans covering unit\-level and system\-level requirements, then write the test cases and assertions that validate them
• Build and maintain regression suites using VCS, NC, or MTI, analyzing coverage gaps and driving metrics toward 100% functional closure
• Debug complex protocol interactions and RTL issues across multi\-layer verification stacks, working directly with design engineers to resolve root causes
• Automate verification flows using Perl, TCL, or Python to streamline regressions, coverage extraction, and reporting
• Contribute to methodology improvements, including VIP development, formal verification integration, and UVM framework enhancements
• Collaborate with global verification teams across Bangalore, the US, and other sites to align on verification strategies and