ASIC PHYSICAL VERIFICATION ENGINEER at vhunt4u — Chennai | Apply 2026 | 3rangaV
ASIC PHYSICAL VERIFICATION ENGINEER
Full-timevia scraped
Job Description
- *Work Location** : Chennai, Cambridge, Bangalore, London, San Jose**Work Expertise** : 10 Years \- 15 Years**Desired Profile** :
- Bachelor's / Master's degree in engineering from EEE / E\&C with expertise in ASIC PV
- Expertise in physical verification with full signoff ownership
- Expertise in DRC, LVS and ESD verification methodologies
- Expertise in Calibre, ICV (IC Validator) or Pegasus
- Expertise in foundry DRM : able to read, interpret, and implement complex rule decks
- Expertise in advanced nodes 4nm and below
- Expertise in using AI agents to drive automation across verification flows and tapeout signoff
- *Job Specs** :* Own and execute full\-chip DRC, LVS, ESD, and antenna signoff using Calibre, ICV, or Pegasus
Develop, maintain, and optimize physical verification flows for advanced node SoC and 3D IC designs
Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changesDebug and resolve complex DRC/LVS violations across hierarchical full\-chip designsPerform ESD verification — validate protection strategies, current paths, and CDM/HBM complianceDrive tapeout readiness by coordinating signoff across block and top\-level design teamsEngage directly with foundry teams to resolve DRM ambiguities and waiver requestsLeverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflowsJob Overview
- Job type
- Full-time
- Work mode
- On-site
- Location
- Chennai
- Posted
- 22h ago
- Source
- Scraped