ASIC/RTL Design Engineer – CPU Design Verification

• *Job Summary**

We are seeking a highly motivated Design Verification Engineer to join our CPU Verification team. The ideal candidate will contribute to the verification of next\-generation processor architectures by debugging complex failures, developing verification infrastructure, enhancing automation, and improving overall verification quality. This role offers exposure to CPU microarchitecture, simulation and emulation environments, and advanced verification methodologies.

• *Required Skills**

· 3–5 years of experience in ASIC/SoC Design Verification.

· Strong understanding of

o Computer Architecture fundamentals (x86, ARM, or similar architectures)

o Digital Design concepts

o RTL design and verification principles

· Experience with verification environments using

o SystemVerilog

o C\+\+

o UVM/OVM methodologies (preferred)

· Strong debugging, analytical, and problem\-solving skills.

· Experience working with simulation and/or emulation platforms.

· Proficiency in one or more scripting languages

o Python

o Perl

o Shell

o Ruby

• *Preferred Qualifications**

· Experience in CPU or processor subsystem verification.

· Understanding of CPU microarchitecture, including

o Pipeline stages

o Execution units

o Cache hierarchy

o Memory subsystems

· Familiarity with assembly\-level programming and debug.

· Exposure to performance, functional, or architectural verification methodologies.

· Awareness of ML/AI applications in verification and debug workflows.

• *Key Responsibilities**

· Debug and triage failures from simulation and emulation environments at the CPU core and subsystem levels.

· Analyze and resolve issues across key processor components including:

o Frontend (Fetch/Decode)

o Execution and Load/Store Units

o Floating Point Units

o Cache and Memory Hierarchy

· Debug and analyze test cases written in Assembly language and C\+\+\-based verification environments.

· Develop and enhance automation, debug, and triage tools using Python, Perl, Ruby, Shell scripting, and C\+\+.

· Contribute to stimulus development through

o Directed test creation

o Random test generation

o Regression improvement initiatives

· Improve debug infrastructure and reduce debug turnaround time.

· Collaborate with architecture, design, verification, and validation teams to identify coverage gaps and improve test quality.

· Investigate bug escapes and implement preventive verification strategies.

· Drive automation and process improvement initiatives to increase verification efficiency.

· Support post\-silicon debug and validation activities when required.

· Explore opportunities to leverage ML/AI techniques for debug and verification productivity improvements.

Pay: ₹1,000,000\.00 \- ₹1,500,000\.00 per year

Work Location: In person