Senior /Staff AMS Layout engineer-DPG-LPDDR

Job ID

JR103641

• *Our vision is to transform how the world uses information to enrich life for** ***all*****.**

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

• **Own and drive custom analog and mixed\-signal layout** for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy
• **3\-12 years of solid hands\-on experience** in custom analog and high\-speed layout design, with proven expertise in implementing and delivering critical analog blocks and LPDDR/high\-speed interfaces at advanced technology nodes
• Lead **high\-speed LPDDR (LPDDRx) interface layout execution**, solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes
• Architect and implement **scalable array\-based layout strategies** for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi\-channel scalability
• Drive **integration of custom digital and mixed\-signal blocks** within the PHY (training logic, calibration engines, test/debug circuitry), ensuring optimal clocking, congestion management, and isolation from sensitive analog regions
• Lead **layout\-aware co\-design with circuit teams**, enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective
• Establish robust **power distribution, grounding, and isolation strategies**, including guard rings, deep N\-well usage, decoupling, and domain separation for high\-speed and analog\-sensitive regions
• Own **physical verification and signoff closure**:

+ DRC/LVS, parasitic extraction, and simulation correlation

+ Ensure silicon\-accurate performance for analog\-intensive and high\-speed LPDDR blocks

• Drive **post\-layout optimization and ECOs**, resolving margin, yield, and manufacturability challenges while ensuring JEDEC compliance
• Collaborate cross\-functionally with **architecture, circuit, verification, and silicon debug teams** to enable first\-pass silicon success and high\-volume manufacturability
• Own and drive **PPA optimization**, delivering measurable improvements in power efficiency, area utilization, and performance
• Mentor engineers and contribute to **layout methodologies and best practices**, including VXL\-compatible flows, design reviews, and continuous improvement initiatives
• Leveraging Artificial Intelligence
• Leverage **automation and advanced techniques**:

+ Apply scripting (SKILL/Python/TCL) to improve productivity

+ Use AI/ML concepts as a value\-add for data\-driven optimization and layout automation

• *About Micron Technology, Inc.**

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life *for all*. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high\-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

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